1. Field of the Invention
This invention relates to a data decoding apparatus and method and data reproduction apparatus, and more particularly, is applicable to such apparatus that reproduces moving pictures digitalized and recorded in a disc.
2. Description of the Related Art
There have been discs on which moving pictures are digitalized and recorded at a variable rate according to, for example, the moving pictures expert group (MPEG) standard.
The MPEG specifies three types of pictures for picture data: I pictures (Intra-Pictures) that are intra-frame coded pictures, P pictures (Predictive-Pictures) that are inter-frame forward predictive coded pictures, and B pictures (Bidirectionally predictive-Pictures) that are bidirectionally predictive coded pictures. These three types of pictures form a group of pictures (GOP).
Although the MPEG standard is also applied to voice data, for example, the additive transform acoustic coding (ATAC) is also used to digitalize and compressing-code voice data. ATRAC is a trademark.
FIG. 1 shows a data decoding apparatus 1 for reproducing data recorded on a disc at a variable rate. The data decoding apparatus 1 uses a pickup 3 to irradiate an optical disc 2 with laser beams to reproduce data recorded thereon from reflected beams. A reproduced signal S1 output from the pickup 3 is input to and demodulated in a demodulating circuit 6 in a decoding circuit system 5 controlled by a system controller 4. The data, demodulated by the demodulating circuit 6, is input to an error correction code (ECC) circuit 8 via a sector detection circuit 7, in which error detection""s and corrections are carried out.
If the sector detection circuit 7 has not properly detected the sector numbers or addresses assigned to the sectors of the optical disc 2, a sector number error signal is output to a track jump determination circuit 9. If uncorrectable data has been found, the ECC circuit 8 outputs an error signal to the track jump determination circuit 9. Error-corrected data is sent out from the ECC circuit 8 to a ring buffer memory 10 and recorded thereon.
A ring buffer control circuit 11 then reads the address of each sector from the output from the sector detection circuit 7, and specifies the write address (hereinafter, referred to as a write pointer WP) on the ring buffer memory 10 which corresponds to the first address.
The ring buffer control circuit 11, controlled by the system controller 4, specifies a read address (hereinafter, referred to as a read pointer RP) for the data that has been written to the ring buffer memory 10, based on a code request signal R10 from a multiplexed data separation circuit 13 located beyond the ring buffer control circuit, and reads data from the read pointer RP to supply it to the multiplexed data separation circuit 13.
A header separation circuit 14 in the multiplexed data separation circuit 13 separates a pack header and a packet header from the data supplied from the ring buffer memory 10, and supplies them to a separation circuit control circuit 15. The separation circuit control circuit 15 sequentially and cyclically switches and connects the input terminal G and output terminals (switched terminals) H1 and H2 of a switching circuit 16 according to the stream ID (identifier) information of the packet header supplied from the header separation circuit 11, and correctly separates the time-division-multiplexed data to supply it to a code buffer.
A video code buffer 17 then generates a code request R1 to the multiplexed data separation circuit 13 using the remaining amount of internal code buffer. The video code buffer 17 stores received data. It also receives a code request R1 from a video decoder 18 and outputs the data therein. The video decoder 18 reproduces a video signal from the data supplied and outputs it from its output OUT1.
An audio code buffer 19 generates a code request R2 to the multiplexed data separation circuit 13 using the remaining amount of internal code buffer. The audio code buffer 19 stores received data. It also receives a code request R2 from an audio decoder 20 and outputs the data therein. The audio decoder 20 reproduces an audio signal from the data supplied and outputs it from its output OUT2.
As described above, the video decoder 18 requests data from the video code buffer 17, the video code buffer 17 requests data from the multiplexed data separation circuit 13, and the multiplexed data separation circuit 13 requests data from the ring buffer control circuit 11.
In this case, the data flows from the ring buffer memory 10 in the direction opposite to that of the requests.
Data decoding carried out by the demodulating circuit system 5 is described. The reproduced signal S1 read from the disc 2 is converted into a binary signal by the demodulating circuit 6 using RF processing. Then a rough servomechanism acts on the reproduced signal S1 based on the measurement result of the mark length of the signal S1. When the sector detection circuit 7, as an interface to the system controller 4, detects an EFM+ sync header, a PLL (Phase Locked Loop) servomechanism acts on the sync header. When several sync headers are subsequently and continuously detected, data S2, which has been EFM+-demodulated, is deinterleaved.
As shown in FIG. 2, the EFM+-demodulated data S2 is sent out to the ECC circuit 8, stored in a RAM 24, and then ECC-decoded by ECC decoders 25, 27, and 29 for three sequences C11 (the first C1 sequence), C2, and C12 (the second C1 sequence) including C1/C2 convolutional Reed and Solomon codes (CIRC Plus).
The ECC circuit 8 carries out ECC-decoding by, for example, writing the EFM+-demodulated data S2 to the RAM 24 in the order of 00, 01, . . . , A8, and A9 (EFM+ Write) and once two frames of EFM+ demodulated data has been stored in the RAM 24, transferring the data in frame 1 to the ECC decoder 25 in the order of 00xe2x80x2, 02xe2x80x2, . . . , A8xe2x80x2, 01, 03, . . . , A9 to ECC-decode the deinterleaved C1 sequence of data, as shown in FIG. 3.
Errors are corrected by reading the error positions and correction patterns from the ECC decoder 25, reading the erroneous data from the RAM 24 (C1 read), exclusively logically adding this data to the correction patterns, and writing the resultant data back to the RAM 26 (C1 Write), as shown in FIG. 4. The ECC decoder 25 ECC-decodes the C1 sequence of data over a C2 code sequence length.
Once the C1 sequence data has been ECC-decoded over a C2 code sequence length, the C2 sequence of data can then be ECC-decoded. The data on the RAM 26 is read on the order of 00xe2x80x2, 01xe2x80x2, 02xe2x80x2, 03xe2x80x2, . . . , A9 xe2x80x2(C2 read), and the ECC decoder 27 ECC-decodes this C2 sequence of data. An uncorrectable error flag for each frame can be transferred to the next ECC decoder in synchronism with the data so as to execute erasure corrections. The C1 uncorrectable error flag is used to apply an erasure correction to the C2 sequence of data. The error correction operation is as in C1.
As shown in FIG. 5, once the results of the ECC-decoding of the C2 sequence of data have been written to the RAM 28 (C2 Write) and the C2 sequence of data has been ECC-decoded over a C1 code sequence length, the C12 sequence of data can then be ECC-decoded, and the ECC-decoder 29 ECC-decodes the C12 sequence of data read in the order of 00xe2x80x2, 01, 02, 03, . . . , A9 (C12 read).
The C2 uncorrectable error flag is used to apply an erasure correction to the C12 sequence of data. Once the error correction of the C12 data has been finished, the results of the ECC-decoding of the C12 sequence of data is written to a RAM 30 in the order of 00, 01, 02, 03, . . . , A9, as shown in FIG. 6. The decoded ECC C11, C2, and C12 sequence of data is thus stored in the RAM 30 and then read in the order of 00, 01, 02, 03, . . . , A9 (OUT read). The data is then descrambled and sent out to the ring buffer memory 10 to write required sector data thereto.
A desired sector, to which output data requested to be read belongs, is detected by picking up a sector address from the reproduction data stored in a different memory from the memory which is used for the ECC decoding. That is, a memory (RAM 24) used for deinterleaving data which is interleaved at a previous stage and memories (RAM 26, 28, and 30) used for ECC decoding are assigned so that the sector address is positioned at the head for each sector address, in order to detect the sector address. In this way, the sector address is detected from the reproduction data read out on the memory, and is used as position information at the time of access to the optical disc 2 by the system controller 4.
In actual, the ring buffer control circuit 11 compares and determines the detected sector address with the desired sector address set by the system controller 4. If the detected sector address coincides to the desired sector address, an ECC decoded data S10 which has been ECC decoded at the ECC circuit 8 is written in the ring buffer memory 10.
In this ECC decoding method, after a sector ahead of the sector by several sectors is detected at the disc access taking interleave of the ECC into account, the EFM+-demodulated reproduction data is written so that the start frame of the memory used for ECC decoding corresponds to the head of the sector, and the ECC decoding is carried out to write the decoded data in the ring buffer memory 10.
In the case where the interleaved coded data is decoded, the time lag for time required for the ECC decoding occurs between the sector address recognition for the disc access by the system controller 4 and the sector address which is output after data of the sector is ECC decoded. Therefore, there is a problem that since the sector is not ECC decoded at the time of recognizing the sector address during the disc access due to the time lag, it can not be determined whether or not the ECC decoded data S10 is certainly written in the ring buffer memory 10.
In addition, in the case where the interleaved coded data is decoded, there is a problem that since a memory for detecting a desired sector and a storage medium such as a memory used for the ECC decoding are necessary separately, the capacity of a memory becomes comparatively large.
Further, to recognize the sector, the deinterleaved data is first written in a RAM 24 being a memory used for decoding in an arbitrary sector unit. At this time, the reproduction data read out from an optical disc 2 is stored so that the head of the sector corresponds to the head of the memory, so that the capacity of the memory has to have N times capacity of the sector.
Further, at the stage of writing data in the ring buffer memory 10, since the head of the decoded data is not always the head of the sector, the desired sector has to be detected again from the ECC decoded data S10 stored in a memory (RAM 30) used the ECC decoding. Therefore, other circuit for recognizing data of the desired sector address has to be provided in addition to a circuit for recognizing the sector address at the time of the disc address. Thus there is a problem that the configuration of a circuit is complicated.
In view of the foregoing, an object of this invention is to provide a data decoding apparatus and method and a data reproduction apparatus which can reduce the capacity of the memory for ECC decoding and can speedily access to the desired sector.
The foregoing object and other objects of the invention have been achieved by the provision of a data decoding apparatus for decoding coded data which is recorded in a recording medium. The data decoding apparatus comprises: a memory used for decoding for storing coded data and decoded data which the coded data is decoded; a data information detecting circuit for detecting data information of data to be read from decoded data which is generated in the middle of decoding the coded data; a data information storage means for storing the data information; and a data output control circuit for controlling the output of decoded data on the basis of the data information.
Further, according to the present invention, in a data decoding method for decoding coded data which is recorded in a recording medium, the coded data read from the recording medium is stored in a memory used for decoding, data information of data to be read is detected from decoded data which is generated in the middle of decoding the coded data to be stored, and the output of the decoded data is controlled based on the data information.
By this, in the middle of decoding the coded data recorded in the recording medium, the data information of data to be read is detected and stored in the data information storage means, thereby the output of the decoded data can be controlled based on the data information independent of the decoding of the coded data.
Furthermore, according to the present invention, a data reproduction apparatus for reading out and reproducing video signals and audio signals being coded data recorded in the recording medium, comprises a data decoding apparatus having: a memory used for decoding for storing coded data and decoded data which the coded data is decoded; a data information detecting circuit for detecting data information of data to be read from the decoded data which is generated in the middle of decoding the coded data; a data information storage means for storing data information; and a data output control circuit for controlling the output of the decoded data based on the data information independent of the decoding of the coded data.
By this, in the middle of decoding the coded data recorded in the recording medium, data information of data to be read is detected and stored in the data information storage means, thereby the output of the decoded data can be controlled based on the data information independent of the decoding of the coded data, thus the coded data can be speedily reproduced.
The nature, principle and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters.